1. Field of the Invention
The present invention relates to an apparatus for correcting skew caused during slow-motion reproduction in a video cassette recorder or the like.
2. Description of the Prior Art
In the conventional skew correctors known heretofore, it is customary that memory write and read cycles are executed alternately with an address counter reset at each picture start point in such a manner that a write address corresponds to an input signal, and a read operation is performed periodically regardless of such reset to consequently correct the skew.
In such conventional skew correctors where individual addresses are needed for write and read respectively, it follows that normal write and read cycles are individually necessary for the memory write and read. Accordingly the time required for memory write and read cycles is rendered twice that as compared with the execution of write or read alone, hence necessitating twice the number of parallel data lines for data converted by a serial-parallel conversion circuit in case the sampling period is shorter than the memory write or read cycle time. Thus, the number of required memories is doubled eventually.
FIG. 9 shows a serial-parallel conversion circuit employed in a conventional skew corrector, and FIG. 10 is a timing chart showing waveforms of signals in the circuit of FIG. 9. The reference symbols representing such waveforms correspond to those used in FIG. 9.
The operation of such a circuit is performed in the following manner. First, a video signal fed via an input terminal 10 is quantized and sampled by an A/D converter 30. FIG. 10 shows an exemplary case where the sampling frequency is three times the write or read cycle. Subsequently the data DI quantized by the A/D converter 30 are converted into six parallel data by eleven D flip-flops (DFFs) 32 responsive to six phase-shifted clock pulses .phi.11-.phi.16. The parallel data Qll thus obtained are written in six memories 1 . . . during the low level state of a signal RW.
The signal RW serves to selectively switch read and write cycles in such a manner that its high level and low level correspond respectively to a read cycle and a write cycle. During the high level state of the signal RW, the data are read out from the memories 17 as M11 and are once held in six DFFs 33 as Q12. Subsequently the data Q12 are processed to resume the original sampling frequency by six tri-state buffers 34 responsive to clock pulses .phi.11-.phi.16 to obtain a serial data DO. The data DO is converted into a video signal by a D/A converter 31, and the video signal is outputted from an output terminal 11.
In such known serial-parallel conversion circuit, a total of six memories 17 are required whereas the sampling frequency is three times as high as the write or read cycle.